1. Field of the Invention
The invention relates to a method of fabricating semiconductor memory devices employing floating gates, and more particularly, to a method of fabricating memory devices employing floating gates having an improved tunneling oxide.
2. Description of the Prior Art
One class of semiconductor memory devices employs floating gates; that is, gates which are completely surrounded by an insulating layer, such as a silicon oxide. The presence or absence of charge in the floating gates represents binary information. These are called electrically programmable read only memories (EPROM). EEPROMS are erasable electrically programmable read only memories. A tunneling oxide, necessary for the erase function of the cell, is situated below the floating gate of the memory cell. Typically, the tunneling oxide is formed by a thermal oxidation process. The inventors have found that the tunneling oxide is thinner at the edges of the thick oxide areas. This oxide edge thinning is thought to occur because there is less oxygen under the thick oxide areas to join in the oxidation reaction; thus, the growth rate of the tunneling oxide there will be lower than in the bare silicon area.
FIG. 1 illustrates a semiconductor substrate 10 on which have been formed thick oxide areas 11. Tunnel oxide 13 is grown on the surface of the substrate between the thick oxide areas 11, as shown in FIG. 2. The thickness T1 of the tunnel oxide 13 in the center portion is greater than the thickness T2 of the tunnel oxide at the edge portion by about 10 Angstroms. The thin oxide portion at the edge of the thick oxide is weak and easily damaged by charges, plasma, electric fields, etc. The weak thinning oxide will also form more surface states and charge or hole trapping centers. All of these effects reduce reliability, especially in EEPROM applications.
A similar tunneling oxide thinning has been observed adjacent to a field oxide region. This thinning is due to stress. Workers in the art have tried to improve this stress-related thinning by using a chemically vapor deposited (CVD) stacked gate oxide. This method is used in the U.S. Pat. No. 5,219,774 to Vasche and is illustrated in FIGS. 3-5. FIG. 3 illustrates a semiconductor substrate 10 in which Field OXide regions 12 have been formed. An oxide film 13 is formed by thermal oxidation, as shown in FIG. 4. It can be seen that oxide thinning occurs at the edges adjacent to the field oxide regions 12. Referring now to FIG. 5, an oxide film 14 is deposited over the thermal oxide layer 13 by chemical vapor deposition (CVD) and then densified. This smooths the film edge and improves the stress induced oxide thinning. However, the thinning effect caused by the thermal oxidation growth rate difference is not reduced.
U.S. Pat. Nos. 5,516,713 and 5,427,970 to Hsue et al, 5,352,619 to Hong, and 5,411,904 to Yamauchi et al teach methods of forming small tunneling oxide windows wherein tunneling oxide is thermally grown. U.S. Pat. No. 5,122,847 to Kamiya et al teaches forming a tunneling oxide by CVD at a high temperature of 700.degree. C. or more for a film with a higher breakdown current density.